Over the past years in the field of semiconductor circuits, clock speeds have generally increased, while at the same time demands have increased for ever lower power consumption by such circuits, as semiconductor circuits have found increasing uses in portable applications, where battery drain is an issue. An area of significant concern relates to busses, which are conduction lines that generally gather and distribute signals to and from a multiplicity of sources and targets. These conductors tend to have relatively high reactance, due to their size, and therefore require significant current to drive signals with sufficient speed to meet the performance requirements of the circuits in which they are used. While conventional driver circuits may have very low static power dissipation, nonetheless, when driving such high reactance buses the dynamic power dissipation can be considerable.
One solution to this problem is to provide for reduced voltage swing drivers to the buses, while providing receivers for bus signals that translate the low bus voltage swing signals to the level required by the receiving circuitry. For discussions of this approach, see, e.g., “A Novel Reduced Swing CMOS BUS Interface Circuit for high speed low power VLSI systems,” by R. Golshan and B. Haroun, 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, Vol. 4, London, England, U.K., May 30–Jun. 2, 1994, pages 351–354, and “Low-Power CMOS/BiCMOS Drivers and Receivers for On-Chip Interconnects,” by A. Bellaouar, I. S. Abu-Khater and M. I. Elmasry, IEEE Journal of Solid-State Circuits, Vol. 30, No. 6., June 1995, pages 696–700, “An Efficient Low-Power Bus Architecture,” by A. Rjoub, S. Nikolaidis, O. Koufopavlou and T. Stouraitis, 1997 IEEE International Symposium on Circuits and Systems, Jun. 9–12, 1997, Hong Kong, pages 1864–1867, and “Efficient Drivers, Receivers and Repeaters for Low Power CMOS Bus Architectures,” by A. Rjoub and O. Koufopavlou, Proceedings of ICECS, Vol. 2, IEEE 1999, pages 789–794.
One of the receiver circuits developed to translate the low bus voltage swing signals to the level required by the receiving circuitry using this approach is the “up full swing voltage” receiver. Such a receiver is described in the article, cited above, by A. Bellaouar et al. FIG. 1a is the same as FIG. 4a of that article, and shows such a receiver. This circuit is designed to convert an input signal Vin having a reduced swing, e.g. having a high level of Vdd−Vtn and a low level of ground (GND) to an output signal Vout having full swing, where Vdd is the power supply voltage and Vtn is the threshold voltage of an N-type MOS device in the circuit. The diode D in the circuit of FIG. 1a may be implemented as a PMOS transistor having its gate connected to its drain. A problem with the circuit of FIG. 1a is that when the voltage of Vin is less than Vdd−Vtn, a static current flows in the path including diode D and PMOS transistor P11. Thus, in low voltage applications, undesirable static power is wasted, which is contrary to the purpose of low voltage circuit design.